COMPUTER ENGINEERING • HARDWARE SYSTEMS
Computer engineering student focused on embedded systems, robotics, PCB-level problem solving, and the careful translation of sensor data into useful motion.
BIO
I’m a Computer Engineering student at Rutgers University with a bias toward systems I can physically build and test. From leading electrical design for open-source quadruped robots to engineering custom macro decks, I thrive in the messy middle between CAD, custom PCBs, and physical hardware.
CURRENT TOOLCHAIN
KiCad
PCB Design
Verilog
Python
C++
Java
MATLAB
Onshape
Engineering tools: soldering, 3D printing, NVIDIA Isaac Sim, Jetson Nano, Onshape, SolidWorks, and MATLAB. Programming: Verilog, C++, Java, and Python.
SELECTED BUILDS
Physical systems, documented as working prototypes.
06 / LAB INDEX
RBT-01
Open-source quadruped
Affordable quadruped platform featuring custom PCB designs and hardware-in-the-loop (HIL) testing for gait stability and sensor fusion.
PCB Design • Isaac Sim • Jetson Nano
MOB-02
Vision-controlled bionic hand
A 3D-printed, tendon-driven robotic hand actuated by real-time computer vision. It utilizes MediaPipe to extract live webcam hand landmarks, translating user gestures into precise multi-axis servo control via a serial-linked Arduino.
Python • MediaPipe • 3D Printing • Arduino • C++
PCB-03
Autonomous micromouse
Miniature robotics platform built from scratch to navigate complex mazes under strict constraints using infrared sensors and custom pathfinding logic.
PCB Design • C++ • Embedded Logic
MOB-02
Custom macro interface
Programmable peripheral combining a 15-inch secondary display, mechanical switches, and a 3D-printed enclosure for direct desktop control.
SolidWorks • UI • 3D Printing
CTL-04
Digital traffic controller
State-machine-driven four-way traffic system simulating discrete logic circuits to manage precise signal timing without high-level microcontrollers.
Verilog • Logic Design • Simulation
MECH-05
Filtration rate simulator
Mathematical model simulating fluid dynamics and pore-clogging coefficients to optimize multi-stage water purification system lifespans by 75%.
MATLAB • Data Analysis • Modeling
PWR-06
Single-cycle RISC-V CPU
In-development: Custom processor architecture mapping datapath logic, memory access, and ALU design using hardware description languages.
Architecture • Verilog • CPU Design